1. Field of the Invention
The present invention relates to semiconductor packages and methods of fabricating the same, and, more particularly, to a wafer-level semiconductor package used for 3D packaging and a method of fabricating the same.
2. Description of Related Art
Wafer level packaging (WLP) involves packaging and testing integrated circuits at a wafer level. After a WLP process, wafer dicing can be performed to obtain a plurality of WLP packages substantially of the same size as dies. Since having advantages of small size and good electrical performance, the WLP packages have been widely applied to meet the miniaturization requirement of electronic devices.
Generally, WLP packages have fan-in and fan-out structures that meet the requirement of I/O counts and ball pitches. Further, by using through silicon via (TSV) or plated through hole (PTH) technologies, 3D WLP packages have been developed to meet the continuously increased density of circuits and miniaturization of package sizes.
Referring to FIG. 1A, to fabricate a conventional semiconductor package 1, a plurality of through holes 120 are formed in an encapsulant 12 encapsulating a plurality of semiconductor elements 10.
Referring to FIG. 1B, a plurality of conductive through holes 15 are formed in the through holes 120 by electroplating.
Referring to FIG. 1C, a dielectric layer 16, a circuit layer 17 and an insulating layer 18 are sequentially formed on the encapsulant 12.
However, an overburden may occur on the encapsulant during formation of the conductive through holes, and a metal layer may be formed on exposed conductive pads of the semiconductor elements. As such, a chemical mechanical polishing (CMP) process must be performed to remove the metal layer on the conductive pads so as to prevent short circuits from occurring between the conductive pads, thereby increasing the fabrication cost. In addition, since a redistribution layer (RDL) requires forming a dielectric layer before forming a circuit layer, the fabrication cost is further increased.
Therefore, there is a need to provide a semiconductor package and a fabrication method thereof so as to overcome the above-described drawbacks.